1. Field of the Invention
The present invention relates to packaging substrates and package structures, and, more particularly, to a packaging substrate and a package structure having a plurality of stacked dielectric layers and circuit layers.
2. Description of Related Art
Flip-chip technologies facilitate to reduce chip package area, signal path and so on, and therefore have been widely used for chip packaging, such as chip scale package (CSP) and multi-chip module (MCM).
FIG. 1 is a cross-sectional view of a conventional flip-chip 1 substrate. Referring to FIG. 1, the substrate 1 has a plurality of dielectric layers 11 and a plurality circuit layers 12 alternately stacked with each dielectric layers 11. If each dielectric layer 11 in a packaging substrate 1 that has four dielectric layers 11 is 40 μm thick, a thickness sum of the four dielectric layers 11 is 160 μm.
However, during a temperature cycle test of a flip-chip packaging process, warpage easily occurs to the package substrate due to a big CTE (Coefficient of Thermal Expansion) mismatch between the chip and the package substrate, a surface area of the packaging substrate being too large, or asymmetrical heating. Consequently, it becomes difficult to form good joints between conductive bumps around an outer periphery of the chip and contacts of the package substrate, thereby reducing the product yield.
The warpage problem may be alleviated by increasing the thickness of the dielectric layer, which, however, also increases the overall thickness of the packaging substrate and unable to meet the low-profiled, compact-sized requirements.
Accordingly, there is an urgent need to solve the drawbacks encountered in the prior art.